1. Field of the Invention
The present invention relates to a receiving circuit for digital data transmitted by wireless.
2. Description of the Related Art
There exists such a form of digital data exchange that a plurality of mobile stations and a fixed station (base station) make bit-serial communication with each other. A receiving circuit reproduces clock signals from the received data and carries out processing of the received data such as determination thereof according to the clock signal.
In the case of communication between a plurality of stations, a time-division multiplex communication is carried out for the purpose of efficient use of time. In the time-division multiplex communication, clock signals are reproduced from the received data of each slot, then the data and the clock signals are combined and sent to the circuits in the following stage.
In addition a diversity antenna is used for the purpose of achieving more accurate data reception. The receiving circuit reproduces the clock signal by selecting the data received on the antenna which is in more favorable receiving condition.
FIGS. 1(a), (b) are block circuit diagrams illustrative of the constitution of a receiving circuit of a prior art. Radio signals received on antennas 1, 2 are inputted to demodulators 3, 4, respectively. The demodulators 3, 4 are provided with clock reproduction/data extraction circuits 31, 32, . . . , 44 which are allocated to the respective slots of the received signals. The demodulators 3, 4 demodulate the received signals, and the clock reproduction/data extraction circuits 31, 32, . . . , 44 extract the data of-the respective slots from the demodulated signals, while reproducing a clock signal by using the bit-serial data thus extracted.
Reproduced clock signals C11, . . . , C14 of the respective slots on the side of the antenna 1 and the demodulator 3 are inputted to a selector 51. And received data D11, . . . , D14 of the respective slots on the side of the antenna 1 and the demodulator 3 are inputted to a selector 52.
Reproduced clock signals C21, . . . , C24 of the respective slots on the side of the antenna 2 and tile demodulator 4 are inputted to a selector 53. And received data D21, . . . , D24 of the respective slots on the side of the antenna 2 and the demodulator 4 are inputted to a selector 54.
A time-division timing control circuit 58 sends receive enabling signal successively to the clock reproduction/data extraction circuits 31 (41), 32 (42), 33 (43) and 34 (44) and, at the same time, sends such a signal to the selector 52 (54) that causes the selector 52 (54) to select the received data D11, . . . D14 (D21, . . . D24) which are outputted successively by the clock reproduction/data extraction circuits 31 (41), 32 (42), 33 (43) and 34 (44) upon receipt of the receive enabling signal, and sends such a signal to the selector 51 (53) that causes the selector 51 (53) to select the reproduced clock signals C11, . . . , C14 (C21, . . . , C24) which are outputted successively by the clock reproduction/data extraction circuits 31 (41), 32 (42), 33 (43) and 34 (44) upon receipt of the receive enabling signal.
Outputs from the selectors 52, 54 are sent to a selector 56 and outputs from tile selectors 51, 53 are sent to a selector 55. Selection of either the output from the selector 55 or from the selector 56 is done by selecting either a combination of the received data and the reproduced clock signal from the antenna 1 or a combination of the received data and the reproduced clock signal from the antenna 2, by means of the antenna switching signal which is outputted by a diversity controller 57 which monitors the signal intensities received on the antennas and selects the antenna which gives signals of higher intensity. Circuits that follow determine the received data using the reproduced clock signal and carry out other operations.
While selectors 51, 53, 55 switch the reproduced clock signals in such a circuit of the prior art as described above, phase difference between the slots and phase difference between the antennas cause a noise called spike, comprising an oscillation for a short duration, to appear on the output clock signals from the selectors 51, 53, 55 in synchronization with the switching timing. The spike may be mistaken as a rising edge or falling edge of the clock signal, leading to an error when determining the received data.